DRAMs include memory storage cells that store data on capacitors. Charge or lack of charge on these capacitors is used to represent logic "1" or "0" data states. The capacitors are susceptible to charge leaking off (or on) over periods of time, typically milliseconds, and must therefore be refreshed or restored to their representative data states periodically.
DRAMs are constructed of or organized into one or several memory cell arrays or subarrays consisting of rows and columns (which correspond to word lines and bit lines). When a row is selected during an active cycle, all of the cells along that row are sensed and restored. An active cycle is when the memory cells are accessed by word lines to read, write or refresh, for example. Then a precharge cycle is performed, which is not part of an active cycle, to ready the memory array to enter another active cycle.
To refresh the entire array, also done during an active cycle, generally only the rows need to be selected. All the capacitors of the memory cells along a row or portion of a row are refreshed when that row is addressed. (That is, all of the columns are operative during refresh.) Row selection can be done by cycling through all the row addresses with a row address strobe signal ("RAS"), or any standard read/write cycle. For example, column address strobe before row address strobe (CAS before RAS or "CBR") cycling provides the row address internally from refresh counters so that each row will be selected and refreshed.
The external signal RAS, supplied by a system and provided externally of the memory package, is generally used to control many functions of a DRAM. One of its uses is analogous to a chip select signal as used by other types of chips. If the external signal RAS remains low for a long enough time, all of the active cycle clocks will operate in proper sequence, terminate and then wait for a user command, such as reading or writing new data by toggling CAS, or returning to precharge by bringing RAS high.
As illustrated in FIGS. 1(a)-(k), active cycle events of conventional DRAMs are started with the falling edge of an external signal RAS (see FIG. 1(a)). For a refresh active cycle, the falling edge of the external signal RAS triggers an internal signal RAS' (FIGS. 1(a) and (b)). Internal signal RAS' is the main control signal of the internal functions of a memory part, and is illustrated as active low.
The falling edge of RAS' triggers an internal address signal ADD, which triggers a precharge clock signal .phi..sub.p and a shorting clock signal .phi..sub.SH (FIGS. 1(b), (c), (e) and (f)). Internal address signal ADD (shown as active high in FIG. 1(c)) allows the address, supplied externally or by internal counters, to be input to memory row decoders of the memory. Precharge clock signal .phi..sub.p is a representation of one or more precharge clocks used to trigger precharge functions of the memory device. As shown in FIG. 1(e), precharge clock signal .phi..sub.p is active high, that is, when .phi..sub.p is high, the memory circuitry is precharged. Shorting clock signal .phi..sub.SH is used to trigger the shorting of the bit lines during precharge. The bit lines are shorted together so that small amounts of charge from the memory cells can be sensed when a memory cell is selected. Shorting clock signal .phi..sub.SH is illustrated in FIG. 1(f) as being an active high clock. That is, when .phi..sub.SH is high, the bit lines are shorted.
Internal address signal ADD triggers a word line signal WL as shown in FIGS. 1(c) and (d). Essentially, word line signal WL is generated from the decoded address that internal address signal ADD allowed to pass to the row decoder. WL is one of many word lines or rows in a memory cell array (for example a typical 4 meg DRAM can be configured as 1024 rows by 4096 columns). Word line signal WL triggers a sense clock signal .phi..sub.s (FIGS. 1(d) and (g)). Sense clock signal .phi..sub.S represents one or more sense clock signals which are used to enable sense amplifiers of the memory to read corresponding bit lines.
As seen in FIGS. 1(g)-(i), sense clock signal .phi..sub.S triggers a latch signal LN and a latch signal LP, which have active states that are low and high, respectively. Latch signals LN and LP are sense amplifier driver signals that control the bit line sense amplifiers. When the sense amplifiers latch, each bit line connected thereto is driven either high or low, depending on the voltage of that bit line (or the differential in voltage between the two bit lines). Driving the LP and LN lines high or low serves to latch the logic value present on the bit lines as shown in FIG. 1(h)-(j) which will restore full levels back into the memory cells.
Typically, a restore finished signal RF is triggered when latch signal LP reaches a predetermined level. At this point the memory array is ready to enter a precharge cycle.
A precharge cycle generally vAIl not start as long as the external signal RAS remains low. When the user or system causes the external signal RAS to go high, if the signal RF is high, then the precharge cycle begins. The precharge cycle will complete itself if the external signal RAS remains high long enough. The right side of FIGS. 1(a)-(k) shows a timing sequence for a precharge cycle for a conventional DRAM. External signal RAS triggers internal signal RAS' to become inactive. FIGS. 1(a), (b). RAS' triggers internal address signal ADD to become inactive and precharge clock signal .phi..sub.p to become active, as shown in FIGS. 1(b), (c) and (e). Precharge clock signal .phi..sub.p triggers word line signal WL to become inactive. See FIGS. 1(d) and (e).
FIGS. 1(d) and (f) show that word line signal WL triggers the shorting clock signal .phi..sub.SH to become active and sense clock signal .phi..sub.S inactive. Shorting clock signal .phi..sub.SH triggers the latch signals LN and LP to become inactive, and bit line and bit line bar signals BL/BL to a precharged state, as shown in FIGS. 1(f) and (h)-(j). The precharged state of bit line and bit line bar lines BL/BL is typically VCC/2 (where VCC is a power supply voltage).
FIGS. 1(a)-(k) show one cycle for refreshing and precharging one row address. It is important to note that external signal RAS is controlled by the user or system. After a row is accessed and restored, the user or system must change the state of external signal RAS . When external signal RAS changes, the precharge cycle is triggered. After the precharge cycle is completed, the memory waits until the user or system changes the state of external signal RAS to start yet another active cycle.
For conventional DRAMs, a time margin is added when specifying how quickly RAS can cycle or change. That is, minimum high and low times for the external signal RAS are specified for worst case operating conditions. At nominal or typical operating conditions, the time margin is wasted since internally the memory is operating faster. This time could be saved if the memory would, for at least refreshing purposes, automatically enter precharge when the active cycle is completed and then automatically enter the active cycle when precharge is completed. This would tend to minimize the cycle time for any given operating voltage and temperature.
Conventional DRAMs are driven or controlled by memory controller devices that are not part of the memory chip. These devices control the functions of the memory, such as read, write and refresh. Memory controller devices are typically quite complex to furnish the refresh operation for a DRAM. In the instance where the memory part uses CAS before RAS refreshing, the memory controller must supply column and row address strobes for each row that is to be refreshed. For a 4 megabit memory array, the memory controller would have to provide 1024 CAS before RAS cycles to refresh the whole memory.
In one prior patent to Malik and Celio, U.S. Pat. No. 4,503,525 entitled "COMMON CIRCUIT FOR DYNAMIC REFRESH AND SYSTEM CLOCK FUNCTION," a memory is controlled by a RAM controller. That patent seeks to use the dedicated system clock (which is external to both the RAM and the RAM controller) to control the refresh operation of the RAM, in addition to its basic use as a time-of-day counter.
It is known also to use counters located on the RAM chip itself for refreshing. For example, some DRAMs have a battery back-up mode where a refresh counter is used in the process of addressing rows for refreshing the DRAM, in a low power operation. Such systems are not directed to high speed operations but rather to conserving power. See, for example, Konishi et al. "A 38 ns 4 Mb DRAM with a Battery Back-up (BBU) Mode," ISSCC 90 pp. 230 et seq. ("The BBU mode is a kind of self refresh mode . . . As a result all memory cells are refreshed within 4096 cycles per 256 msec in the BBU mode.")
Therefore, it is a general object of the present invention to overcome the above-mentioned drawbacks and reduce complexity.
Another object of the present invention is to make semiconductor memories, especially DRAMS, more accessible to typical computer systems by reducing the time required for refresh operations.
An object of this invention is to create an operation, which I call a "burst refresh mode" (BRM) in order to refresh the data in a given DRAM in as little time as possible.
Whereas many users employ CAS before RAS refreshes to restore the data, another object of the invention is to allow the CAS before RAS cycles to be fewer in number or faster in cycle time, or both, so that the user has less of what the art refers to as "refresh overhead."